1. Field of the Invention
This invention is related to the field of microprocessors and, more particularly, to interrupt handling mechanisms within microprocessors.
2. Description of the Relevant Art
Modern computer systems and the software which runs thereon demand a high performance interrupt structure order to operate efficiently. Interrupts are often used to switch between tasks, and so a multi-tasking operating system benefits from a high performance interrupt structure. A xe2x80x9cmulti-taskingxe2x80x9d operating system is configured to run multiple programs concurrently. Additionally, interrupts provide a means for an electronic device external to the microprocessor to request attention from the operating system. Modern day computer system are including increasing numbers of these electronic devices, prompting the need for a high performance interrupt structure.
Interrupts cause a microprocessor within the computer system to suspend execution of a task and to execute a specific software routine (referred to as an interrupt service routine) comprising a set of instruction. The interrupt is typically unrelated to the instruction being executed by the microprocessor at the time the interrupt occurs. Instead, the interrupt is caused by an external device requiring software attention. For example, a buffer within an input/output device may fill with data to be transferred to another device or to memory. Many other sources for interrupts are well-known to the skilled artisan.
The instruction being executed by the microprocessor at the time the interrupt occurs are referred to herein as a xe2x80x9ctaskxe2x80x9d. A task may be a portion of a program, an operating system routine, or even another interrupt service routine.
Because the interrupt is normally unrelated to the task being performed by the microprocessor and is asynchronous to the task itself, the interrupt service routine is executed in such a way that the task may be resumed. In order to resume the task, the xe2x80x9ccontextxe2x80x9d within which the task is executing may be saved to memory. The context includes register values associated with the task when the task is interrupted. Additionally, the context may include the values within any memory locations that may be accessible to the task. Handling of an interrupt via saving the context and establishing a context for the interrupt service routine is referred to as a xe2x80x9ctask switchxe2x80x9d. After saving the context, the interrupt service routine is executed. Upon completion of the interrupt service routine, the context is restored to the microprocessor and the task is resumed. Since the restored context is identical to the context when the task was interrupted, the task executed normally. In other words, the interrupt has no effect on the results of executing the task. Instead, only the time required to execute the task is affected.
Often, an interrupt service routine will only require access to a few registers within the register set to perform its function. In this case, full context save is not necessary since some registers will not be modified by the interrupt service routine. Instead, only those storage locations which must be changed in order to fetch the instructions within the interrupt service routine need be saved prior to beginning execution of the interrupt service routine. For example, in the x86 architecture the EIP register and CS segment register (which define the address and segment of the instructions to be fetched and executed) and the flags register (which is modified by many of the x86 instructions) are saved. These values are pushed onto the stack defined by the x86 architecture when the task switch method of interrupt handling is not being used.
When the task switch method of interrupt handling is not in use, an interrupt service routine saves the values stored within registers which it employs to carry out its intended function. This method of interrupt handling is referred to as an interrupt gate or trap gate in the x86 architecture, depending on whether or not the interrupt service routine may itself be interrupted.
Regardless of the whether or not the task switch method of interrupt handling is in use, the interrupt service routine must be located in memory. Since there may be multiple sources of interrupts, many computer systems provide a mechanism for identifying one of multiple interrupt service routines. The computer system thus provides flexibility to programmer in that a particular interrupt service routine may be tailored to the needs of a particular device.
One method for providing the address of the interrupt service routine for a given interrupt is for the microprocessor to request an interrupt vector from another electronic device in the system. An xe2x80x9cinterrupt vectorxe2x80x9d is a number which is indicative of a particular interrupt service routine. For example, the interrupt vector may be an index into an interrupt descriptor table which provides information identifying the address of the associated interrupt service routine. As used herein, an interrupt descriptor table is a set of memory locations which specifies interrupt information for each interrupt vector. xe2x80x9cInterrupt informationxe2x80x9d refers to information identifying an interrupt service routine in memory. This interrupt information may include segment information identifying the segment in which the interrupt service routine lies, as well as an offset within the segment identifying the beginning of the interrupt service routine. Furthermore, interrupt information may include attributes of the segment.
A segment is a mechanism for providing address translation. Many microprocessor architecture specify a memory model that involves address translation. Before an address identifying an instruction or data in memory is presented to the memory, that address is modified by the microprocessor. During the modification, attributes of the segment may be compared to attributes of the task and to the nature of the access to ensure that the task is performing an appropriate action within the segment. As used herein, the term xe2x80x9csegmentxe2x80x9d refers to a portion of a main memory. xe2x80x9cSegment attributesxe2x80x9d refer to attributes associated with the segment. It is noted that a segment may be defined as an instruction (or code) segment containing instructions, a data segment, or an interrupt segment. Segment attributes may include protection information identifying the allowable access to the segment, a base address identifying the beginning of the segment, a limit identifying the size of the segment, and a selector identifying the entry within the table storing other segment attributes.
Segment information, such as segment attributes, is often stored in a set of memory locations referred to as a descriptor table. For example, the x80 microprocessor architecture defines the aforementioned interrupt descriptor table as well as a global descriptor table. The global descriptor table may contain segment information regarding code, data, or interrupt segments. The interrupt descriptor table contains segment information regarding interrupt segments. It is noted that, in one embodiment, a portion of the interrupt segment information is located in the interrupt descriptor table. The remainder of the interrupt segment information is located in the global descriptor table.
Unfortunately, transferring interrupt information from the memory locations comprising descriptor tables to the microprocessor often requires many clock cycles to complete. Furthermore, the interrupt information identifies a segment, and additional information related to the segment is fetched from the global descriptor table. Ever more clock cycles are used to perform the global descriptor table fetch. As used herein, a clock cycle refers to the amount of time required by portions of the microprocessor to perform their functions. The results of each function are stored in a storage location (e.g. a register or memory) according to a clock signal defining the clock cycle and may be used by another function in the next clock cycle. The bus used by a microprocessor to communicate with other electrical devices may operate according to a different clock cycle than the microprocessor itself. The clock cycle associated with the bus is often referred to as the bus clock cycle. The clock cycles and bus clock cycles spent awaiting the interrupt information may reduce performance of the microprocessor, since the interrupt service routine cannot be located until the interrupt information is transferred and processed. A microprocessor configured to perform interrupts in a higher performance fashion is desired.
The problems outlined above are in large part solved by a microprocessor configured with an interrupt descriptor cache. The interrupt descriptor cache is configured to store interrupt information associated with a plurality of interrupt vectors. Prior to fetching interrupt information from a main memory of a computer system, the present microprocessor searches the interrupt descriptor cache. If the interrupt information is stored therein, the address of the interrupt service routine is formed from the stored interrupt information. Advantageously, the interrupt service routine may be entered more quickly by determining the address of the interrupt service routine internally to the microprocessor. Clock cycles saved due to the reduced interrupt latency are available for performing tasks. Performance of the microprocessor and a computer system employing the microprocessor may be advantageously increased.
The interrupt descriptor cache is additionally configured to monitor memory accesses for updates to the interrupt information stored therein. If a memory location storing interrupt information is updated, then the interrupt descriptor cache invalidates any storage locations which may be storing the information. In this manner, the interrupt information stored within the interrupt descriptor cache is maintained coherent with respect to any changes that may be made to the interrupt information.
In one embodiment, the interrupt descriptor cache includes fewer storage locations than the number of possible interrupt vectors within the microprocessor architecture. In many cases, computer systems into which the microprocessor is employed limit the number of unique interrupt vectors which may be defined. Advantageously, the interrupt descriptor cache may include storage locations sufficient to store a small number of interrupt vectors while still retaining much of the performance advantage that a larger storage may engender. Silicon area used to implement the interrupt descriptor cache may be reduced without constituting a performance impact.
Broadly speaking, the present invention contemplates a microprocessor comprising an interrupt descriptor cache and a control unit. The interrupt descriptor cache includes a plurality of storage locations. Each one of the plurality of storage locations is configured to store interrupt information associated with an interrupt vector. The control unit is configured to cause the interrupt information to be stored into the interrupt descriptor cache and further configured to transfer the interrupt information across a bus.
The present invention still further contemplates a method for storing interrupt information associated with an interrupt vector within a microprocessor comprising several steps. Interrupt information is transferred from a main memory coupled to the microprocessor into the microprocessor upon a first occurrence of the interrupt vector. The interrupt information is stored within an interrupt descriptor cache and retrieved from the interrupt descriptor cache upon a second occurrence of the interrupt vector.
The present invention still further contemplates a computer system comprising a microprocessor coupled to an interrupt controller. The microprocessor is configured to store interrupt information associated with a plurality of interrupt vectors. The interrupt controller is configured to convey the interrupt vector to the microprocessor according to a plurality of interrupt request signals.